An interface block in SystemVerilog can use a clocking block to specify the timing of synchronous signals relative to the clock.

• Signals in a clocking block are driven and sampled synchronously, ensuring correct timing interaction between the testbench and design.
• Clocking blocks are primarily used in testbenches, but they can also be used to create abstract synchronous models.

Key Points

• An interface can include multiple clocking blocks, one per clock domain.
• Each clocking block contains a single clock expression, such as:

@(posedge clk)
@(posedge clk1 or negedge clk2)

• You can specify a clock skew using the default statement.

• Default behavior:

  • Inputs are sampled just before the design executes.
  • Outputs are driven during the same time slot.

This synchronization prevents race conditions between the testbench and the DUT.
Once a clocking block is defined, your testbench can use:

@my_interface.cb

instead of explicitly writing out the clock and edge.
If the clock or edge changes, only the clocking block definition needs to be updated — not the entire testbench.

Interface with a Clocking Block

interface arb_if(input bit clk);
  logic [1:0] grant, request;
  logic reset;

  // Declare clocking block
  clocking cb @(posedge clk);
    output request;
    input grant;
  endclocking

  // Modport for testbench
  modport TEST (clocking cb, output reset);

  // Modport for DUT
  modport DUT (input request, reset, output grant);
endinterface

Explanation

• cb is the clocking block that activates on the positive edge of the clock.
• Signal directions (input, output) are relative to the modport using them.
  • request → output in TEST modport.
  • grant → input in TEST modport.